-- Vhdl test bench created from schematic 
-- My Documents\FPGA\counter3\c3schem.sch 
-- by J.Beale Sun Apr 10 23:15:47 2011
-- Test Bench for CPLD TIC (Time Interval Counter)  
-- counter should run at START pulse, until STOP pulse


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY c3schem_c3schem_sch_tb IS
END c3schem_c3schem_sch_tb;
ARCHITECTURE behavioral OF c3schem_c3schem_sch_tb IS 

   COMPONENT c3schem
   PORT( START	:	IN	STD_LOGIC; 
          STOP	:	IN	STD_LOGIC; 
          CLK	:	IN	STD_LOGIC; 
          DOUT	:	OUT	STD_LOGIC_VECTOR (15 DOWNTO 0); 
          RESET	:	IN	STD_LOGIC; 
          START_S1B	:	OUT	STD_LOGIC; 
          START_S3B	:	OUT	STD_LOGIC; 
          STOP_S1B	:	OUT	STD_LOGIC; 
          STOP_S3B	:	OUT	STD_LOGIC; 
          START_S2B	:	OUT	STD_LOGIC);
   END COMPONENT;

   SIGNAL START	:	STD_LOGIC;
   SIGNAL STOP	:	STD_LOGIC;
   SIGNAL CLK	:	STD_LOGIC;
   SIGNAL DOUT	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
   SIGNAL RESET	:	STD_LOGIC;
   SIGNAL START_S1B	:	STD_LOGIC;
   SIGNAL START_S3B	:	STD_LOGIC;
   SIGNAL STOP_S1B	:	STD_LOGIC;
   SIGNAL STOP_S3B	:	STD_LOGIC;
   SIGNAL START_S2B	:	STD_LOGIC;
	
	constant PERIOD : time := 10 ns;       -- 100 MHz clock

BEGIN

   UUT: c3schem PORT MAP(
		START => START, 
		STOP => STOP, 
		CLK => CLK, 
		DOUT => DOUT, 
		RESET => RESET, 
		START_S1B => START_S1B, 
		START_S3B => START_S3B, 
		STOP_S1B => STOP_S1B, 
		STOP_S3B => STOP_S3B, 
		START_S2B => START_S2B
   );

 --clock gen
	 CLK_PROCESS : PROCESS is
     BEGIN
	   CLK <='1';
      wait for PERIOD/2; 
		CLK <='0';
	  wait for PERIOD/2; 
	  END PROCESS;

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
	
   BEGIN
	  START <= '0';
	  STOP  <= '0'; 
	  RESET <= '0';
	  
	  wait for PERIOD*0.1;
	  RESET <= '1';
	  
	  wait for PERIOD*1.5;
	  RESET <= '0';
	  wait for PERIOD*3.2;  -- not synchronous to CLK
	  START <= '1';							 -- start the counter
	  wait for PERIOD*1.3;
	  START <= '0';
	  wait for PERIOD*3.2;
	  STOP <= '1';								 -- stop the counter
	  wait for PERIOD*1.1;
	  STOP <= '0';
	  wait for PERIOD * 2;
	  RESET <= '1';							 -- reset everything
	  WAIT for PERIOD*1.4;
	  RESET <= '0'; 
	
	  wait for PERIOD*1.2;  -- not synchronous to CLK
	  START <= '1';							 -- start the counter
	  wait for PERIOD*1.3;
	  START <= '0';
	  wait for PERIOD*3.2;
	  STOP <= '1';								 -- stop the counter
	  wait for PERIOD*1.1;
	  STOP <= '0';
	  wait for PERIOD * 2;
	  RESET <= '1';							 -- reset everything
	  WAIT for PERIOD*1.5;
	  RESET <= '0'; 
	
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;