Core Clock Configuration Register (3-35) CCCR 0x00000107 00000000 00000000 00000001 00000111 CCCR_L 7 CM crystal freq to memory freq multiplier CCCR_M 0 CM memory freq to run mode freq multiplier CCCR_N 2 CM run mode freq to turbo freq multiplier Clock Enable Register (3-36) CKEN 0x00d9d223 00000000 11011001 11010010 00100011 CKEN_0 1 CM PWM0 clock enabled CKEN_1 1 CM PWM1 clock enabled CKEN_2 0 CM AC97 clock enabled CKEN_3 0 CM SSP clock enabled CKEN_5 1 CM STUART clock enabled CKEN_6 0 CM FFUART clock enabled CKEN_7 0 CM BTUART clock enabled CKEN_8 0 CM I2S clock enabled CKEN_11 0 CM USB clock enabled CKEN_12 1 CM MMC clock enabled CKEN_13 0 CM FIPC clock enabled CKEN_14 1 CM I2C clock enabled CKEN_16 1 CM LCD clock enabled Oscillator Configuration Register (3-38) OSCC 0x00000003 00000000 00000000 00000000 00000011 OSCC_OOK 1 CM 32.768 kHz oscillator enabled and stabilized OSCC_OON 1 CM 32.768 kHz oscillator enabled GPIO Pin Level Register 0 (4-7) GPLR0 0x87c97bff 10000111 11001001 01111011 11111111 GPLR0_0 1 GPIO 0 level (A/C Power detect (1=present) GPLR0_1 1 GPIO 1 level (Power Button (0=pressed)) GPLR0_2 1 GPIO 2 level GPLR0_3 1 GPIO 3 level GPLR0_4 1 GPIO 4 level GPLR0_5 1 GPIO 5 level GPLR0_6 1 GPIO 6 level GPLR0_7 1 GPIO 7 level GPLR0_8 1 GPIO 8 level GPLR0_9 1 GPIO 9 level GPLR0_10 0 GPIO 10 level (Right-hand LED (0=on)) GPLR0_11 1 GPIO 11 level (LCD backlight) GPLR0_12 1 GPIO 12 level (CIF_DD<7>) GPLR0_13 1 GPIO 13 level GPLR0_14 1 GPIO 14 level (wifi reset) GPLR0_15 0 GPIO 15 level (wifi power) GPLR0_16 1 GPIO 16 level (KP_MKIN<5>) GPLR0_17 0 GPIO 17 level (KP_MKIN<6>) GPLR0_18 0 GPIO 18 level GPLR0_19 1 GPIO 19 level GPLR0_20 0 GPIO 20 level GPLR0_21 0 GPIO 21 level GPLR0_22 1 GPIO 22 level GPLR0_23 1 GPIO 23 level GPLR0_24 1 GPIO 24 level GPLR0_25 1 GPIO 25 level GPLR0_26 1 GPIO 26 level GPLR0_27 0 GPIO 27 level GPLR0_28 0 GPIO 28 level GPLR0_29 0 GPIO 29 level GPLR0_30 0 GPIO 30 level GPLR0_31 1 GPIO 31 level GPIO Level Register 1 (4-8) GPLR1 0x005fde19 00000000 01011111 11011110 00011001 GPLR1_32 1 GPIO 32 level GPLR1_33 0 GPIO 33 level GPLR1_34 0 GPIO 34 level GPLR1_35 1 GPIO 35 level GPLR1_36 1 GPIO 36 level GPLR1_37 0 GPIO 37 level GPLR1_38 0 GPIO 38 level GPLR1_39 0 GPIO 39 level GPLR1_40 0 GPIO 40 level GPLR1_41 1 GPIO 41 level GPLR1_42 1 GPIO 42 level GPLR1_43 1 GPIO 43 level GPLR1_44 1 GPIO 44 level GPLR1_45 0 GPIO 45 level GPLR1_46 1 GPIO 46 level GPLR1_47 1 GPIO 47 level GPLR1_48 1 GPIO 48 level GPLR1_49 1 GPIO 49 level GPLR1_50 1 GPIO 50 level GPLR1_51 1 GPIO 51 level GPLR1_52 1 GPIO 52 level GPLR1_53 0 GPIO 53 level GPLR1_54 1 GPIO 54 level GPLR1_55 0 GPIO 55 level GPLR1_56 0 GPIO 56 level GPLR1_57 0 GPIO 57 level GPLR1_58 0 GPIO 58 level GPLR1_59 0 GPIO 59 level GPLR1_60 0 GPIO 60 level GPLR1_61 0 GPIO 61 level GPLR1_62 0 GPIO 62 level GPLR1_63 0 GPIO 63 level GPIO Level Register 2 (4-8) GPLR2 0x7f1e0eb5 01111111 00011110 00001110 10110101 GPLR2_64 1 GPIO 64 level GPLR2_65 0 GPIO 65 level GPLR2_66 1 GPIO 66 level GPLR2_67 0 GPIO 67 level GPLR2_68 1 GPIO 68 level GPLR2_69 1 GPIO 69 level GPLR2_70 0 GPIO 70 level GPLR2_71 1 GPIO 71 level GPLR2_72 0 GPIO 72 level GPLR2_73 1 GPIO 73 level GPLR2_74 1 GPIO 74 level GPLR2_75 1 GPIO 75 level GPLR2_76 0 GPIO 76 level GPLR2_77 0 GPIO 77 level GPLR2_78 0 GPIO 78 level GPLR2_79 0 GPIO 79 level GPLR2_80 0 GPIO 80 level GPLR2_81 1 GPIO 81 level GPLR2_82 1 GPIO 82 level GPLR2_83 1 GPIO 83 level GPLR2_84 1 GPIO 84 level GPIO Direction Register 0 (4-9) GPDR0 0xdbfcee00 11011011 11111100 11101110 00000000 GPDR0_0 0 GPIO 0 i/o direction (1=output) GPDR0_1 0 GPIO 1 i/o direction (1=output) GPDR0_2 0 GPIO 2 i/o direction (1=output) GPDR0_3 0 GPIO 3 i/o direction (1=output) GPDR0_4 0 GPIO 4 i/o direction (1=output) GPDR0_5 0 GPIO 5 i/o direction (1=output) GPDR0_6 0 GPIO 6 i/o direction (1=output) GPDR0_7 0 GPIO 7 i/o direction (1=output) GPDR0_8 0 GPIO 8 i/o direction (1=output) GPDR0_9 1 GPIO 9 i/o direction (1=output) GPDR0_10 1 GPIO 10 i/o direction (1=output) GPDR0_11 1 GPIO 11 i/o direction (1=output) GPDR0_12 0 GPIO 12 i/o direction (1=output) GPDR0_13 1 GPIO 13 i/o direction (1=output) GPDR0_14 1 GPIO 14 i/o direction (1=output) GPDR0_15 1 GPIO 15 i/o direction (1=output) GPDR0_16 0 GPIO 16 i/o direction (1=output) GPDR0_17 0 GPIO 17 i/o direction (1=output) GPDR0_18 1 GPIO 18 i/o direction (1=output) GPDR0_19 1 GPIO 19 i/o direction (1=output) GPDR0_20 1 GPIO 20 i/o direction (1=output) GPDR0_21 1 GPIO 21 i/o direction (1=output) GPDR0_22 1 GPIO 22 i/o direction (1=output) GPDR0_23 1 GPIO 23 i/o direction (1=output) GPDR0_24 1 GPIO 24 i/o direction (1=output) GPDR0_25 1 GPIO 25 i/o direction (1=output) GPDR0_26 0 GPIO 26 i/o direction (1=output) GPDR0_27 1 GPIO 27 i/o direction (1=output) GPDR0_28 1 GPIO 28 i/o direction (1=output) GPDR0_29 0 GPIO 29 i/o direction (1=output) GPDR0_30 1 GPIO 30 i/o direction (1=output) GPDR0_31 1 GPIO 31 i/o direction (1=output) GPIO Direction Register 1 (4-9) GPDR1 0xffa3aaab 11111111 10100011 10101010 10101011 GPDR1_32 1 GPIO 32 i/o direction (1=output) GPDR1_33 1 GPIO 33 i/o direction (1=output) GPDR1_34 0 GPIO 34 i/o direction (1=output) GPDR1_35 1 GPIO 35 i/o direction (1=output) GPDR1_36 0 GPIO 36 i/o direction (1=output) GPDR1_37 1 GPIO 37 i/o direction (1=output) GPDR1_38 0 GPIO 38 i/o direction (1=output) GPDR1_39 1 GPIO 39 i/o direction (1=output) GPDR1_40 0 GPIO 40 i/o direction (1=output) GPDR1_41 1 GPIO 41 i/o direction (1=output) GPDR1_42 0 GPIO 42 i/o direction (1=output) GPDR1_43 1 GPIO 43 i/o direction (1=output) GPDR1_44 0 GPIO 44 i/o direction (1=output) GPDR1_45 1 GPIO 45 i/o direction (1=output) GPDR1_46 0 GPIO 46 i/o direction (1=output) GPDR1_47 1 GPIO 47 i/o direction (1=output) GPDR1_48 1 GPIO 48 i/o direction (1=output) GPDR1_49 1 GPIO 49 i/o direction (1=output) GPDR1_50 0 GPIO 50 i/o direction (1=output) GPDR1_51 0 GPIO 51 i/o direction (1=output) GPDR1_52 0 GPIO 52 i/o direction (1=output) GPDR1_53 1 GPIO 53 i/o direction (1=output) GPDR1_54 0 GPIO 54 i/o direction (1=output) GPDR1_55 1 GPIO 55 i/o direction (1=output) GPDR1_56 1 GPIO 56 i/o direction (1=output) GPDR1_57 1 GPIO 57 i/o direction (1=output) GPDR1_58 1 GPIO 58 i/o direction (1=output) GPDR1_59 1 GPIO 59 i/o direction (1=output) GPDR1_60 1 GPIO 60 i/o direction (1=output) GPDR1_61 1 GPIO 61 i/o direction (1=output) GPDR1_62 1 GPIO 62 i/o direction (1=output) GPDR1_63 1 GPIO 63 i/o direction (1=output) GPIO Direction Register 2 (4-9) GPDR2 0x9fe1ffff 10011111 11100001 11111111 11111111 GPDR2_64 1 GPIO 64 i/o direction (1=output) GPDR2_65 1 GPIO 65 i/o direction (1=output) GPDR2_66 1 GPIO 66 i/o direction (1=output) GPDR2_67 1 GPIO 67 i/o direction (1=output) GPDR2_68 1 GPIO 68 i/o direction (1=output) GPDR2_69 1 GPIO 69 i/o direction (1=output) GPDR2_70 1 GPIO 70 i/o direction (1=output) GPDR2_71 1 GPIO 71 i/o direction (1=output) GPDR2_72 1 GPIO 72 i/o direction (1=output) GPDR2_73 1 GPIO 73 i/o direction (1=output) GPDR2_74 1 GPIO 74 i/o direction (1=output) GPDR2_75 1 GPIO 75 i/o direction (1=output) GPDR2_76 1 GPIO 76 i/o direction (1=output) GPDR2_77 1 GPIO 77 i/o direction (1=output) GPDR2_78 1 GPIO 78 i/o direction (1=output) GPDR2_79 1 GPIO 79 i/o direction (1=output) GPDR2_80 1 GPIO 80 i/o direction (1=output) GPDR2_81 0 GPIO 81 i/o direction (1=output) GPDR2_82 0 GPIO 82 i/o direction (1=output) GPDR2_83 0 GPIO 83 i/o direction (1=output) GPDR2_84 0 GPIO 84 i/o direction (1=output) GPIO Set Register 0 (4-10) GPSR0 0x00000000 00000000 00000000 00000000 00000000 GPSR0_0 0 GPIO 0 set GPSR0_1 0 GPIO 1 set GPSR0_2 0 GPIO 2 set GPSR0_3 0 GPIO 3 set GPSR0_4 0 GPIO 4 set GPSR0_5 0 GPIO 5 set GPSR0_6 0 GPIO 6 set GPSR0_7 0 GPIO 7 set GPSR0_8 0 GPIO 8 set GPSR0_9 0 GPIO 9 set GPSR0_10 0 GPIO 10 set GPSR0_11 0 GPIO 11 set GPSR0_12 0 GPIO 12 set GPSR0_13 0 GPIO 13 set GPSR0_14 0 GPIO 14 set GPSR0_15 0 GPIO 15 set GPSR0_16 0 GPIO 16 set GPSR0_17 0 GPIO 17 set GPSR0_18 0 GPIO 18 set GPSR0_19 0 GPIO 19 set GPSR0_20 0 GPIO 20 set GPSR0_21 0 GPIO 21 set GPSR0_22 0 GPIO 22 set GPSR0_23 0 GPIO 23 set GPSR0_24 0 GPIO 24 set GPSR0_25 0 GPIO 25 set GPSR0_26 0 GPIO 26 set GPSR0_27 0 GPIO 27 set GPSR0_28 0 GPIO 28 set GPSR0_29 0 GPIO 29 set GPSR0_30 0 GPIO 30 set GPSR0_31 0 GPIO 31 set GPIO Set Register 1 (4-10) GPSR1 0x00000000 00000000 00000000 00000000 00000000 GPSR1_32 0 GPIO 32 set GPSR1_33 0 GPIO 33 set GPSR1_34 0 GPIO 34 set GPSR1_35 0 GPIO 35 set GPSR1_36 0 GPIO 36 set GPSR1_37 0 GPIO 37 set GPSR1_38 0 GPIO 38 set GPSR1_39 0 GPIO 39 set GPSR1_40 0 GPIO 40 set GPSR1_41 0 GPIO 41 set GPSR1_42 0 GPIO 42 set GPSR1_43 0 GPIO 43 set GPSR1_44 0 GPIO 44 set GPSR1_45 0 GPIO 45 set GPSR1_46 0 GPIO 46 set GPSR1_47 0 GPIO 47 set GPSR1_48 0 GPIO 48 set GPSR1_49 0 GPIO 49 set GPSR1_50 0 GPIO 50 set GPSR1_51 0 GPIO 51 set GPSR1_52 0 GPIO 52 set GPSR1_53 0 GPIO 53 set GPSR1_54 0 GPIO 54 set GPSR1_55 0 GPIO 55 set GPSR1_56 0 GPIO 56 set GPSR1_57 0 GPIO 57 set GPSR1_58 0 GPIO 58 set GPSR1_59 0 GPIO 59 set GPSR1_60 0 GPIO 60 set GPSR1_61 0 GPIO 61 set GPSR1_62 0 GPIO 62 set GPSR1_63 0 GPIO 63 set GPIO Set Register 2 (4-11) GPSR2 0x00000000 00000000 00000000 00000000 00000000 GPSR2_64 0 GPIO 64 set GPSR2_65 0 GPIO 65 set GPSR2_66 0 GPIO 66 set GPSR2_67 0 GPIO 67 set GPSR2_68 0 GPIO 68 set GPSR2_69 0 GPIO 69 set GPSR2_70 0 GPIO 70 set GPSR2_71 0 GPIO 71 set GPSR2_72 0 GPIO 72 set GPSR2_73 0 GPIO 73 set GPSR2_74 0 GPIO 74 set GPSR2_75 0 GPIO 75 set GPSR2_76 0 GPIO 76 set GPSR2_77 0 GPIO 77 set GPSR2_78 0 GPIO 78 set GPSR2_79 0 GPIO 79 set GPSR2_80 0 GPIO 80 set GPSR2_81 0 GPIO 81 set GPSR2_82 0 GPIO 82 set GPSR2_83 0 GPIO 83 set GPSR2_84 0 GPIO 84 set GPIO Clear Register 0 (4-11) GPCR0 0x00000000 00000000 00000000 00000000 00000000 GPCR0_0 0 GPIO 0 clear GPCR0_1 0 GPIO 1 clear GPCR0_2 0 GPIO 2 clear GPCR0_3 0 GPIO 3 clear GPCR0_4 0 GPIO 4 clear GPCR0_5 0 GPIO 5 clear GPCR0_6 0 GPIO 6 clear GPCR0_7 0 GPIO 7 clear GPCR0_8 0 GPIO 8 clear GPCR0_9 0 GPIO 9 clear GPCR0_10 0 GPIO 10 clear GPCR0_11 0 GPIO 11 clear GPCR0_12 0 GPIO 12 clear GPCR0_13 0 GPIO 13 clear GPCR0_14 0 GPIO 14 clear GPCR0_15 0 GPIO 15 clear GPCR0_16 0 GPIO 16 clear GPCR0_17 0 GPIO 17 clear GPCR0_18 0 GPIO 18 clear GPCR0_19 0 GPIO 19 clear GPCR0_20 0 GPIO 20 clear GPCR0_21 0 GPIO 21 clear GPCR0_22 0 GPIO 22 clear GPCR0_23 0 GPIO 23 clear GPCR0_24 0 GPIO 24 clear GPCR0_25 0 GPIO 25 clear GPCR0_26 0 GPIO 26 clear GPCR0_27 0 GPIO 27 clear GPCR0_28 0 GPIO 28 clear GPCR0_29 0 GPIO 29 clear GPCR0_30 0 GPIO 30 clear GPCR0_31 0 GPIO 31 clear GPIO Clear Register 1 (4-11) GPCR1 0x00000000 00000000 00000000 00000000 00000000 GPCR1_32 0 GPIO 32 clear GPCR1_33 0 GPIO 33 clear GPCR1_34 0 GPIO 34 clear GPCR1_35 0 GPIO 35 clear GPCR1_36 0 GPIO 36 clear GPCR1_37 0 GPIO 37 clear GPCR1_38 0 GPIO 38 clear GPCR1_39 0 GPIO 39 clear GPCR1_40 0 GPIO 40 clear GPCR1_41 0 GPIO 41 clear GPCR1_42 0 GPIO 42 clear GPCR1_43 0 GPIO 43 clear GPCR1_44 0 GPIO 44 clear GPCR1_45 0 GPIO 45 clear GPCR1_46 0 GPIO 46 clear GPCR1_47 0 GPIO 47 clear GPCR1_48 0 GPIO 48 clear GPCR1_49 0 GPIO 49 clear GPCR1_50 0 GPIO 50 clear GPCR1_51 0 GPIO 51 clear GPCR1_52 0 GPIO 52 clear GPCR1_53 0 GPIO 53 clear GPCR1_54 0 GPIO 54 clear GPCR1_55 0 GPIO 55 clear GPCR1_56 0 GPIO 56 clear GPCR1_57 0 GPIO 57 clear GPCR1_58 0 GPIO 58 clear GPCR1_59 0 GPIO 59 clear GPCR1_60 0 GPIO 60 clear GPCR1_61 0 GPIO 61 clear GPCR1_62 0 GPIO 62 clear GPCR1_63 0 GPIO 63 clear GPIO Clear Register 2 (4-12) GPCR2 0x00000000 00000000 00000000 00000000 00000000 GPCR2_64 0 GPIO 64 clear GPCR2_65 0 GPIO 65 clear GPCR2_66 0 GPIO 66 clear GPCR2_67 0 GPIO 67 clear GPCR2_68 0 GPIO 68 clear GPCR2_69 0 GPIO 69 clear GPCR2_70 0 GPIO 70 clear GPCR2_71 0 GPIO 71 clear GPCR2_72 0 GPIO 72 clear GPCR2_73 0 GPIO 73 clear GPCR2_74 0 GPIO 74 clear GPCR2_75 0 GPIO 75 clear GPCR2_76 0 GPIO 76 clear GPCR2_77 0 GPIO 77 clear GPCR2_78 0 GPIO 78 clear GPCR2_79 0 GPIO 79 clear GPCR2_80 0 GPIO 80 clear GPCR2_81 0 GPIO 81 clear GPCR2_82 0 GPIO 82 clear GPCR2_83 0 GPIO 83 clear GPCR2_84 0 GPIO 84 clear GPIO Raising Edge Detect Enable Register 0 (4-13) GRER0 0x00000000 00000000 00000000 00000000 00000000 GRER0_0 0 GPIO 0 raising edge detect enabled GRER0_1 0 GPIO 1 raising edge detect enabled GRER0_2 0 GPIO 2 raising edge detect enabled GRER0_3 0 GPIO 3 raising edge detect enabled GRER0_4 0 GPIO 4 raising edge detect enabled GRER0_5 0 GPIO 5 raising edge detect enabled GRER0_6 0 GPIO 6 raising edge detect enabled GRER0_7 0 GPIO 7 raising edge detect enabled GRER0_8 0 GPIO 8 raising edge detect enabled GRER0_9 0 GPIO 9 raising edge detect enabled GRER0_10 0 GPIO 10 raising edge detect enabled GRER0_11 0 GPIO 11 raising edge detect enabled GRER0_12 0 GPIO 12 raising edge detect enabled GRER0_13 0 GPIO 13 raising edge detect enabled GRER0_14 0 GPIO 14 raising edge detect enabled GRER0_15 0 GPIO 15 raising edge detect enabled GRER0_16 0 GPIO 16 raising edge detect enabled GRER0_17 0 GPIO 17 raising edge detect enabled GRER0_18 0 GPIO 18 raising edge detect enabled GRER0_19 0 GPIO 19 raising edge detect enabled GRER0_20 0 GPIO 20 raising edge detect enabled GRER0_21 0 GPIO 21 raising edge detect enabled GRER0_22 0 GPIO 22 raising edge detect enabled GRER0_23 0 GPIO 23 raising edge detect enabled GRER0_24 0 GPIO 24 raising edge detect enabled GRER0_25 0 GPIO 25 raising edge detect enabled GRER0_26 0 GPIO 26 raising edge detect enabled GRER0_27 0 GPIO 27 raising edge detect enabled GRER0_28 0 GPIO 28 raising edge detect enabled GRER0_29 0 GPIO 29 raising edge detect enabled GRER0_30 0 GPIO 30 raising edge detect enabled GRER0_31 0 GPIO 31 raising edge detect enabled GPIO Raising Edge Detect Enable Register 1 (4-13) GRER1 0x00000000 00000000 00000000 00000000 00000000 GRER1_32 0 GPIO 32 raising edge detect enabled GRER1_33 0 GPIO 33 raising edge detect enabled GRER1_34 0 GPIO 34 raising edge detect enabled GRER1_35 0 GPIO 35 raising edge detect enabled GRER1_36 0 GPIO 36 raising edge detect enabled GRER1_37 0 GPIO 37 raising edge detect enabled GRER1_38 0 GPIO 38 raising edge detect enabled GRER1_39 0 GPIO 39 raising edge detect enabled GRER1_40 0 GPIO 40 raising edge detect enabled GRER1_41 0 GPIO 41 raising edge detect enabled GRER1_42 0 GPIO 42 raising edge detect enabled GRER1_43 0 GPIO 43 raising edge detect enabled GRER1_44 0 GPIO 44 raising edge detect enabled GRER1_45 0 GPIO 45 raising edge detect enabled GRER1_46 0 GPIO 46 raising edge detect enabled GRER1_47 0 GPIO 47 raising edge detect enabled GRER1_48 0 GPIO 48 raising edge detect enabled GRER1_49 0 GPIO 49 raising edge detect enabled GRER1_50 0 GPIO 50 raising edge detect enabled GRER1_51 0 GPIO 51 raising edge detect enabled GRER1_52 0 GPIO 52 raising edge detect enabled GRER1_53 0 GPIO 53 raising edge detect enabled GRER1_54 0 GPIO 54 raising edge detect enabled GRER1_55 0 GPIO 55 raising edge detect enabled GRER1_56 0 GPIO 56 raising edge detect enabled GRER1_57 0 GPIO 57 raising edge detect enabled GRER1_58 0 GPIO 58 raising edge detect enabled GRER1_59 0 GPIO 59 raising edge detect enabled GRER1_60 0 GPIO 60 raising edge detect enabled GRER1_61 0 GPIO 61 raising edge detect enabled GRER1_62 0 GPIO 62 raising edge detect enabled GRER1_63 0 GPIO 63 raising edge detect enabled GPIO Raising Edge Detect Enable Register 2 (4-13) GRER2 0x00000000 00000000 00000000 00000000 00000000 GRER2_64 0 GPIO 64 raising edge detect enabled GRER2_65 0 GPIO 65 raising edge detect enabled GRER2_66 0 GPIO 66 raising edge detect enabled GRER2_67 0 GPIO 67 raising edge detect enabled GRER2_68 0 GPIO 68 raising edge detect enabled GRER2_69 0 GPIO 69 raising edge detect enabled GRER2_70 0 GPIO 70 raising edge detect enabled GRER2_71 0 GPIO 71 raising edge detect enabled GRER2_72 0 GPIO 72 raising edge detect enabled GRER2_73 0 GPIO 73 raising edge detect enabled GRER2_74 0 GPIO 74 raising edge detect enabled GRER2_75 0 GPIO 75 raising edge detect enabled GRER2_76 0 GPIO 76 raising edge detect enabled GRER2_77 0 GPIO 77 raising edge detect enabled GRER2_78 0 GPIO 78 raising edge detect enabled GRER2_79 0 GPIO 79 raising edge detect enabled GRER2_80 0 GPIO 80 raising edge detect enabled GRER2_81 0 GPIO 81 raising edge detect enabled GRER2_82 0 GPIO 82 raising edge detect enabled GRER2_83 0 GPIO 83 raising edge detect enabled GRER2_84 0 GPIO 84 raising edge detect enabled GPIO Falling Edge Detect Enable Register 0 (4-14) GFER0 0x00000001 00000000 00000000 00000000 00000001 GFER0_0 1 GPIO 0 falling edge detect enabled GFER0_1 0 GPIO 1 falling edge detect enabled GFER0_2 0 GPIO 2 falling edge detect enabled GFER0_3 0 GPIO 3 falling edge detect enabled GFER0_4 0 GPIO 4 falling edge detect enabled GFER0_5 0 GPIO 5 falling edge detect enabled GFER0_6 0 GPIO 6 falling edge detect enabled GFER0_7 0 GPIO 7 falling edge detect enabled GFER0_8 0 GPIO 8 falling edge detect enabled GFER0_9 0 GPIO 9 falling edge detect enabled GFER0_10 0 GPIO 10 falling edge detect enabled GFER0_11 0 GPIO 11 falling edge detect enabled GFER0_12 0 GPIO 12 falling edge detect enabled GFER0_13 0 GPIO 13 falling edge detect enabled GFER0_14 0 GPIO 14 falling edge detect enabled GFER0_15 0 GPIO 15 falling edge detect enabled GFER0_16 0 GPIO 16 falling edge detect enabled GFER0_17 0 GPIO 17 falling edge detect enabled GFER0_18 0 GPIO 18 falling edge detect enabled GFER0_19 0 GPIO 19 falling edge detect enabled GFER0_20 0 GPIO 20 falling edge detect enabled GFER0_21 0 GPIO 21 falling edge detect enabled GFER0_22 0 GPIO 22 falling edge detect enabled GFER0_23 0 GPIO 23 falling edge detect enabled GFER0_24 0 GPIO 24 falling edge detect enabled GFER0_25 0 GPIO 25 falling edge detect enabled GFER0_26 0 GPIO 26 falling edge detect enabled GFER0_27 0 GPIO 27 falling edge detect enabled GFER0_28 0 GPIO 28 falling edge detect enabled GFER0_29 0 GPIO 29 falling edge detect enabled GFER0_30 0 GPIO 30 falling edge detect enabled GFER0_31 0 GPIO 31 falling edge detect enabled GPIO Falling Edge Detect Enable Register 1 (4-14) GFER1 0x00000010 00000000 00000000 00000000 00010000 GFER1_32 0 GPIO 32 falling edge detect enabled GFER1_33 0 GPIO 33 falling edge detect enabled GFER1_34 0 GPIO 34 falling edge detect enabled GFER1_35 0 GPIO 35 falling edge detect enabled GFER1_36 1 GPIO 36 falling edge detect enabled GFER1_37 0 GPIO 37 falling edge detect enabled GFER1_38 0 GPIO 38 falling edge detect enabled GFER1_39 0 GPIO 39 falling edge detect enabled GFER1_40 0 GPIO 40 falling edge detect enabled GFER1_41 0 GPIO 41 falling edge detect enabled GFER1_42 0 GPIO 42 falling edge detect enabled GFER1_43 0 GPIO 43 falling edge detect enabled GFER1_44 0 GPIO 44 falling edge detect enabled GFER1_45 0 GPIO 45 falling edge detect enabled GFER1_46 0 GPIO 46 falling edge detect enabled GFER1_47 0 GPIO 47 falling edge detect enabled GFER1_48 0 GPIO 48 falling edge detect enabled GFER1_49 0 GPIO 49 falling edge detect enabled GFER1_50 0 GPIO 50 falling edge detect enabled GFER1_51 0 GPIO 51 falling edge detect enabled GFER1_52 0 GPIO 52 falling edge detect enabled GFER1_53 0 GPIO 53 falling edge detect enabled GFER1_54 0 GPIO 54 falling edge detect enabled GFER1_55 0 GPIO 55 falling edge detect enabled GFER1_56 0 GPIO 56 falling edge detect enabled GFER1_57 0 GPIO 57 falling edge detect enabled GFER1_58 0 GPIO 58 falling edge detect enabled GFER1_59 0 GPIO 59 falling edge detect enabled GFER1_60 0 GPIO 60 falling edge detect enabled GFER1_61 0 GPIO 61 falling edge detect enabled GFER1_62 0 GPIO 62 falling edge detect enabled GFER1_63 0 GPIO 63 falling edge detect enabled GPIO Falling Edge Detect Enable Register 2 (4-14) GFER2 0x00000000 00000000 00000000 00000000 00000000 GFER2_64 0 GPIO 64 falling edge detect enabled GFER2_65 0 GPIO 65 falling edge detect enabled GFER2_66 0 GPIO 66 falling edge detect enabled GFER2_67 0 GPIO 67 falling edge detect enabled GFER2_68 0 GPIO 68 falling edge detect enabled GFER2_69 0 GPIO 69 falling edge detect enabled GFER2_70 0 GPIO 70 falling edge detect enabled GFER2_71 0 GPIO 71 falling edge detect enabled GFER2_72 0 GPIO 72 falling edge detect enabled GFER2_73 0 GPIO 73 falling edge detect enabled GFER2_74 0 GPIO 74 falling edge detect enabled GFER2_75 0 GPIO 75 falling edge detect enabled GFER2_76 0 GPIO 76 falling edge detect enabled GFER2_77 0 GPIO 77 falling edge detect enabled GFER2_78 0 GPIO 78 falling edge detect enabled GFER2_79 0 GPIO 79 falling edge detect enabled GFER2_80 0 GPIO 80 falling edge detect enabled GFER2_81 0 GPIO 81 falling edge detect enabled GFER2_82 0 GPIO 82 falling edge detect enabled GFER2_83 0 GPIO 83 falling edge detect enabled GFER2_84 0 GPIO 84 falling edge detect enabled GPIO Edge Detect Register 0 (4-15) GEDR0 0x00000000 00000000 00000000 00000000 00000000 GEDR0_0 0 GPIO 0 edge detected GEDR0_1 0 GPIO 1 edge detected GEDR0_2 0 GPIO 2 edge detected GEDR0_3 0 GPIO 3 edge detected GEDR0_4 0 GPIO 4 edge detected GEDR0_5 0 GPIO 5 edge detected GEDR0_6 0 GPIO 6 edge detected GEDR0_7 0 GPIO 7 edge detected GEDR0_8 0 GPIO 8 edge detected GEDR0_9 0 GPIO 9 edge detected GEDR0_10 0 GPIO 10 edge detected GEDR0_11 0 GPIO 11 edge detected GEDR0_12 0 GPIO 12 edge detected GEDR0_13 0 GPIO 13 edge detected GEDR0_14 0 GPIO 14 edge detected GEDR0_15 0 GPIO 15 edge detected GEDR0_16 0 GPIO 16 edge detected GEDR0_17 0 GPIO 17 edge detected GEDR0_18 0 GPIO 18 edge detected GEDR0_19 0 GPIO 19 edge detected GEDR0_20 0 GPIO 20 edge detected GEDR0_21 0 GPIO 21 edge detected GEDR0_22 0 GPIO 22 edge detected GEDR0_23 0 GPIO 23 edge detected GEDR0_24 0 GPIO 24 edge detected GEDR0_25 0 GPIO 25 edge detected GEDR0_26 0 GPIO 26 edge detected GEDR0_27 0 GPIO 27 edge detected GEDR0_28 0 GPIO 28 edge detected GEDR0_29 0 GPIO 29 edge detected GEDR0_30 0 GPIO 30 edge detected GEDR0_31 0 GPIO 31 edge detected GPIO Edge Detect Register 1 (4-16) GEDR1 0x00000000 00000000 00000000 00000000 00000000 GEDR1_32 0 GPIO 32 edge detected GEDR1_33 0 GPIO 33 edge detected GEDR1_34 0 GPIO 34 edge detected GEDR1_35 0 GPIO 35 edge detected GEDR1_36 0 GPIO 36 edge detected GEDR1_37 0 GPIO 37 edge detected GEDR1_38 0 GPIO 38 edge detected GEDR1_39 0 GPIO 39 edge detected GEDR1_40 0 GPIO 40 edge detected GEDR1_41 0 GPIO 41 edge detected GEDR1_42 0 GPIO 42 edge detected GEDR1_43 0 GPIO 43 edge detected GEDR1_44 0 GPIO 44 edge detected GEDR1_45 0 GPIO 45 edge detected GEDR1_46 0 GPIO 46 edge detected GEDR1_47 0 GPIO 47 edge detected GEDR1_48 0 GPIO 48 edge detected GEDR1_49 0 GPIO 49 edge detected GEDR1_50 0 GPIO 50 edge detected GEDR1_51 0 GPIO 51 edge detected GEDR1_52 0 GPIO 52 edge detected GEDR1_53 0 GPIO 53 edge detected GEDR1_54 0 GPIO 54 edge detected GEDR1_55 0 GPIO 55 edge detected GEDR1_56 0 GPIO 56 edge detected GEDR1_57 0 GPIO 57 edge detected GEDR1_58 0 GPIO 58 edge detected GEDR1_59 0 GPIO 59 edge detected GEDR1_60 0 GPIO 60 edge detected GEDR1_61 0 GPIO 61 edge detected GEDR1_62 0 GPIO 62 edge detected GEDR1_63 0 GPIO 63 edge detected GPIO Edge Detect Register 2 (4-16) GEDR2 0x00000000 00000000 00000000 00000000 00000000 GEDR2_64 0 GPIO 64 edge detected GEDR2_65 0 GPIO 65 edge detected GEDR2_66 0 GPIO 66 edge detected GEDR2_67 0 GPIO 67 edge detected GEDR2_68 0 GPIO 68 edge detected GEDR2_69 0 GPIO 69 edge detected GEDR2_70 0 GPIO 70 edge detected GEDR2_71 0 GPIO 71 edge detected GEDR2_72 0 GPIO 72 edge detected GEDR2_73 0 GPIO 73 edge detected GEDR2_74 0 GPIO 74 edge detected GEDR2_75 0 GPIO 75 edge detected GEDR2_76 0 GPIO 76 edge detected GEDR2_77 0 GPIO 77 edge detected GEDR2_78 0 GPIO 78 edge detected GEDR2_79 0 GPIO 79 edge detected GEDR2_80 0 GPIO 80 edge detected GEDR2_81 0 GPIO 81 edge detected GEDR2_82 0 GPIO 82 edge detected GEDR2_83 0 GPIO 83 edge detected GEDR2_84 0 GPIO 84 edge detected GPIO Alternate Function Register 0 Lower (4-17) GAFR0L 0x02000140 00000010 00000000 00000001 01000000 GAFR0L_0 0 GPIO 0 alternate function select GAFR0L_1 0 GPIO 1 alternate function select GAFR0L_2 0 GPIO 2 alternate function select GAFR0L_3 1 GPIO 3 alternate function select GAFR0L_4 1 GPIO 4 alternate function select GAFR0L_5 0 GPIO 5 alternate function select GAFR0L_6 0 GPIO 6 alternate function select GAFR0L_7 0 GPIO 7 alternate function select GAFR0L_8 0 GPIO 8 alternate function select GAFR0L_9 0 GPIO 9 alternate function select GAFR0L_10 0 GPIO 10 alternate function select GAFR0L_11 0 GPIO 11 alternate function select GAFR0L_12 2 GPIO 12 alternate function select GAFR0L_13 0 GPIO 13 alternate function select GAFR0L_14 0 GPIO 14 alternate function select GAFR0L_15 0 GPIO 15 alternate function select GPIO Alternate Function Register 0 Upper (4-18) GAFR0U 0x59188005 01011001 00011000 10000000 00000101 GAFR0U_16 1 GPIO 16 alternate function select GAFR0U_17 1 GPIO 17 alternate function select GAFR0U_18 0 GPIO 18 alternate function select GAFR0U_19 0 GPIO 19 alternate function select GAFR0U_20 0 GPIO 20 alternate function select GAFR0U_21 0 GPIO 21 alternate function select GAFR0U_22 0 GPIO 22 alternate function select GAFR0U_23 2 GPIO 23 alternate function select GAFR0U_24 0 GPIO 24 alternate function select GAFR0U_25 2 GPIO 25 alternate function select GAFR0U_26 1 GPIO 26 alternate function select GAFR0U_27 0 GPIO 27 alternate function select GAFR0U_28 1 GPIO 28 alternate function select GAFR0U_29 2 GPIO 29 alternate function select GAFR0U_30 1 GPIO 30 alternate function select GAFR0U_31 1 GPIO 31 alternate function select GPIO Alternate Function Register 1 Lower (4-18) GAFR1L 0x639420a2 01100011 10010100 00100000 10100010 GAFR1L_32 2 GPIO 32 alternate function select GAFR1L_33 0 GPIO 33 alternate function select GAFR1L_34 2 GPIO 34 alternate function select GAFR1L_35 2 GPIO 35 alternate function select GAFR1L_36 0 GPIO 36 alternate function select GAFR1L_37 0 GPIO 37 alternate function select GAFR1L_38 2 GPIO 38 alternate function select GAFR1L_39 0 GPIO 39 alternate function select GAFR1L_40 0 GPIO 40 alternate function select GAFR1L_41 1 GPIO 41 alternate function select GAFR1L_42 1 GPIO 42 alternate function select GAFR1L_43 2 GPIO 43 alternate function select GAFR1L_44 3 GPIO 44 alternate function select GAFR1L_45 0 GPIO 45 alternate function select GAFR1L_46 2 GPIO 46 alternate function select GAFR1L_47 1 GPIO 47 alternate function select GPIO Alternate Function Register 1 Upper (4-19) GAFR1U 0xaaa03950 10101010 10100000 00111001 01010000 GAFR1U_48 0 GPIO 48 alternate function select GAFR1U_49 0 GPIO 49 alternate function select GAFR1U_50 1 GPIO 50 alternate function select GAFR1U_51 1 GPIO 51 alternate function select GAFR1U_52 1 GPIO 52 alternate function select GAFR1U_53 2 GPIO 53 alternate function select GAFR1U_54 3 GPIO 54 alternate function select GAFR1U_55 0 GPIO 55 alternate function select GAFR1U_56 0 GPIO 56 alternate function select GAFR1U_57 0 GPIO 57 alternate function select GAFR1U_58 2 GPIO 58 alternate function select GAFR1U_59 2 GPIO 59 alternate function select GAFR1U_60 2 GPIO 60 alternate function select GAFR1U_61 2 GPIO 61 alternate function select GAFR1U_62 2 GPIO 62 alternate function select GAFR1U_63 2 GPIO 63 alternate function select GPIO Alternate Function Register 2 Lower (4-19) GAFR2L 0x0aaaaaaa 00001010 10101010 10101010 10101010 GAFR2L_64 2 GPIO 64 alternate function select GAFR2L_65 2 GPIO 65 alternate function select GAFR2L_66 2 GPIO 66 alternate function select GAFR2L_67 2 GPIO 67 alternate function select GAFR2L_68 2 GPIO 68 alternate function select GAFR2L_69 2 GPIO 69 alternate function select GAFR2L_70 2 GPIO 70 alternate function select GAFR2L_71 2 GPIO 71 alternate function select GAFR2L_72 2 GPIO 72 alternate function select GAFR2L_73 2 GPIO 73 alternate function select GAFR2L_74 2 GPIO 74 alternate function select GAFR2L_75 2 GPIO 75 alternate function select GAFR2L_76 2 GPIO 76 alternate function select GAFR2L_77 2 GPIO 77 alternate function select GAFR2L_78 0 GPIO 78 alternate function select GAFR2L_79 0 GPIO 79 alternate function select GPIO Alternate Function Register 2 Upper (4-19) GAFR2U 0x29000308 00101001 00000000 00000011 00001000 GAFR2U_80 0 GPIO 80 alternate function select GAFR2U_81 2 GPIO 81 alternate function select GAFR2U_82 0 GPIO 82 alternate function select GAFR2U_83 0 GPIO 83 alternate function select GAFR2U_84 3 GPIO 84 alternate function select Interrupt Controller Mask Register (4-22) ICMR 0x06920510 00000110 10010010 00000101 00010000 ICMR_IM7 0 Pending IRQ 7 (HWUART) unmasked? ICMR_IM8 1 Pending IRQ 8 (GPIO0) unmasked ICMR_IM9 0 Pending IRQ 9 (GPIO1) unmasked ICMR_IM10 1 Pending IRQ 10 (GPIO2_80) unmasked ICMR_IM11 0 Pending IRQ 11 (USB) unmasked ICMR_IM12 0 Pending IRQ 12 (PMU) unmasked ICMR_IM13 0 Pending IRQ 13 (I2S) unmasked ICMR_IM14 0 Pending IRQ 14 (AC97) unmasked ICMR_IM17 1 Pending IRQ 17 (LCD) unmasked ICMR_IM18 0 Pending IRQ 18 (I2C) unmasked ICMR_IM19 0 Pending IRQ 19 (ICP) unmasked ICMR_IM20 1 Pending IRQ 20 (STUART) unmasked ICMR_IM21 0 Pending IRQ 21 (BTUART) unmasked ICMR_IM22 0 Pending IRQ 22 (FFUART) unmasked ICMR_IM23 1 Pending IRQ 23 (MMC) unmasked ICMR_IM24 0 Pending IRQ 24 (SSP) unmasked ICMR_IM25 1 Pending IRQ 25 (DMA) unmasked ICMR_IM26 1 Pending IRQ 26 (OSMR0) unmasked ICMR_IM27 0 Pending IRQ 27 (OSMR1) unmasked ICMR_IM28 0 Pending IRQ 28 (OSMR2) unmasked ICMR_IM29 0 Pending IRQ 29 (OSMR3) unmasked ICMR_IM30 0 Pending IRQ 30 (RTCCLK) unmasked ICMR_IM31 0 Pending IRQ 31 (RTCALM) unmasked Interrupt Controller Level Register (4-23) ICLR 0x00000000 00000000 00000000 00000000 00000000 ICLR_IL7 0 IRQ 8 (HWUART) generates FIQ? ICLR_IL8 0 IRQ 8 (GPIO0) generates FIQ ICLR_IL9 0 IRQ 9 (GPIO1) generates FIQ ICLR_IL10 0 IRQ 10 (GPIO2_80) generates FIQ ICLR_IL11 0 IRQ 11 (USB) generates FIQ ICLR_IL12 0 IRQ 12 (PMU) generates FIQ ICLR_IL13 0 IRQ 13 (I2S) generates FIQ ICLR_IL14 0 IRQ 14 (AC97) generates FIQ ICLR_IL17 0 IRQ 17 (LCD) generates FIQ ICLR_IL18 0 IRQ 18 (I2C) generates FIQ ICLR_IL19 0 IRQ 19 (ICP) generates FIQ ICLR_IL20 0 IRQ 10 (STUART) generates FIQ ICLR_IL21 0 IRQ 21 (BTUART) generates FIQ ICLR_IL22 0 IRQ 22 (FFUART) generates FIQ ICLR_IL23 0 IRQ 23 (MMC) generates FIQ ICLR_IL24 0 IRQ 24 (SSP) generates FIQ ICLR_IL25 0 IRQ 25 (DMA) generates FIQ ICLR_IL26 0 IRQ 26 (OSMR0) generates FIQ ICLR_IL27 0 IRQ 27 (OSMR1) generates FIQ ICLR_IL28 0 IRQ 28 (OSMR2) generates FIQ ICLR_IL29 0 IRQ 29 (OSMR3) generates FIQ ICLR_IL30 0 IRQ 30 (RTCCLK) generates FIQ ICLR_IL31 0 IRQ 31 (RTCALM) generates FIQ Interrupt Controller Control Register (4-23) ICCR 0x00000001 00000000 00000000 00000000 00000001 ICCR_DIM 0 ONLY enabled and unmasked IRQ bring CPU from idle to run Interrupt Controller IRQ Pending Register (4-24) ICIP 0x00000000 00000000 00000000 00000000 00000000 Interrupt Controller FIQ Pending Register (4-24) ICFP 0x00000000 00000000 00000000 00000000 00000000 Interrupt Controller Pending Register (4-25) ICPR 0x00000000 00000000 00000000 00000000 00000000 ICPR_IS7 0 IRQ 7 (HWUART) pending ICPR_IS8 0 IRQ 8 (GPIO0) pending ICPR_IS9 0 IRQ 9 (GPIO1) pending ICPR_IS10 0 IRQ 10 (GPIO2_80) pending ICPR_IS11 0 IRQ 11 (USB) pending ICPR_IS12 0 IRQ 12 (PMU) pending ICPR_IS13 0 IRQ 13 (I2S) pending ICPR_IS14 0 IRQ 14 (AC97) pending ICPR_IS17 0 IRQ 17 (LCD) pending ICPR_IS18 0 IRQ 18 (I2C) pending ICPR_IS19 0 IRQ 19 (ICP) pending ICPR_IS20 0 IRQ 10 (STUART) pending ICPR_IS21 0 IRQ 21 (BTUART) pending ICPR_IS22 0 IRQ 22 (FFUART) pending ICPR_IS23 0 IRQ 23 (MMC) pending ICPR_IS24 0 IRQ 24 (SSP) pending ICPR_IS25 0 IRQ 25 (DMA) pending ICPR_IS26 0 IRQ 26 (OSMR0) pending ICPR_IS27 0 IRQ 27 (OSMR1) pending ICPR_IS28 0 IRQ 28 (OSMR2) pending ICPR_IS29 0 IRQ 29 (OSMR3) pending ICPR_IS30 0 IRQ 30 (RTCCLK) pending ICPR_IS31 0 IRQ 31 (RTCALM) pending RTC Trim Register (4-30) RTTR 0x00007fff 00000000 00000000 01111111 11111111 RTTR_CK_DIV 7fff RTC Clock Divider Count RTTR_DEL 0 RTC Trim delete Count RTTR_LCK 0 RTC Locking for RTTR RTC Alarm Register (4-30) RTAR 0x001e0248 00000000 00011110 00000010 01001000 RTC Counter Register (4-31) RCNR 0x00000224 00000000 00000000 00000010 00100100 RTC Status Register (4-32) RTSR 0x00000000 00000000 00000000 00000000 00000000 RTSR_AL 0 RTC Alarm Interrupt detected RTSR_HZ 0 RTC Hz Interrupt detected RTSR_ALE 0 RTC Alarm Interrupt Enable RTSR_HZE 0 RTC Hz Interrupt Enable OS Timer Match Register 0 (4-36) OSMR0 0x6a244ec3 01101010 00100100 01001110 11000011 OS Timer Match Register 1 (4-36) OSMR1 0x00000000 00000000 00000000 00000000 00000000 OS Timer Match Register 2 (4-36) OSMR2 0x00000000 00000000 00000000 00000000 00000000 OS Timer Match Register 3 (4-36) OSMR3 0x00000000 00000000 00000000 00000000 00000000 OS Timer Interrupt Enable Register (4-36) OIER 0x00000001 00000000 00000000 00000000 00000001 OIER_E0 1 OS Interrupt for OSMR0 enabled OIER_E1 0 OS Interrupt for OSMR1 enabled OIER_E2 0 OS Interrupt for OSMR2 enabled OIER_E3 0 OS Interrupt for OSMR3 enabled OS Timer Watchdog Match Enable Register (4-37) OWER 0x00000000 00000000 00000000 00000000 00000000 OWER_WME 0 OSMR3 match causes a reset OS Timer Count Register (4-37) OSCR 0x6a2443b8 01101010 00100100 01000011 10111000 OS Timer Status Register (4-38) OSSR 0x00000000 00000000 00000000 00000000 00000000 OSSR_M0 0 OS OSMR0 matched OSCR0 OSSR_M1 0 OS OSMR1 matched OSCR1 OSSR_M2 0 OS OSMR2 matched OSCR2 OSSR_M3 0 OS OSMR3 matched OSCR3 PWM Control Register 0 (4-41) PWMCTL0 0x00000000 00000000 00000000 00000000 00000000 PWMCTL0_PRESCALE 0 PWM0 Prescale Divisor PWMCTL0_SD 0 PWM0 abrupt shutdown PWM Duty Cycle Register 0 (4-42) PWMDUTY0 0x00000000 00000000 00000000 00000000 00000000 PWMDUTY0_DCYCLE 0 PWM0 Duty Cycle PWMDUTY0_FDCYCLE 0 PWM_OUT0 is set high and does not toggle PWM Period Control Register 0 (4-43) PWMPERVAL0 0x00000004 00000000 00000000 00000000 00000100 PWMPERVAL0_PV 4 PWM0 Period Cycle Length PWM Control Register 1 (4-41) PWMCTL1 0x00000000 00000000 00000000 00000000 00000000 PWMCTL1_PRESCALE 0 PWM1 Prescale Divisor PWMCTL1_SD 0 PWM1 abrupt shutdown PWM Duty Cycle Register 1 (4-42) PWMDUTY1 0x00000000 00000000 00000000 00000000 00000000 PWMDUTY1_DCYCLE 0 PWM1 Duty Cycle PWMDUTY1_FDCYCLE 0 PWM_OUT1 is set high and does not toggle PWM Period Control Register 1 (4-43) PWMPERVAL1 0x00000004 00000000 00000000 00000000 00000100 PWMPERVAL1_PV 4 PWM1 Period Cycle Length PWM Control Register 2 (4-41) PWMCTL2 0x00000000 00000000 00000000 00000000 00000000 PWMCTL2_PRESCALE 0 PWM2 Prescale Divisor PWMCTL2_SD 0 PWM2 abrupt shutdown PWM Duty Cycle Register 2 (4-42) PWMDUTY2 0x00000000 00000000 00000000 00000000 00000000 PWMDUTY2_DCYCLE 0 PWM2 Duty Cycle PWMDUTY2_FDCYCLE 0 PWM_OUT2 is set high and does not toggle PWM Period Control Register 2 (4-43) PWMPERVAL2 0x00000004 00000000 00000000 00000000 00000100 PWMPERVAL2_PV 4 PWM2 Period Cycle Length LCD Controller Control Register 0 (7-23) LCCR0 0x05b00af9 00000101 10110000 00001010 11111001 LCCR0_ENB 1 LCD controller enable LCCR0_CMS 0 LCD monochrome operation enable LCCR0_SDS 0 LCD dual panel display enable LCCR0_LDM 1 LCD disable done IRQ disable LCCR0_SFM 1 LCD start of frame IRQ disable LCCR0_IUM 1 LCD fifo underrun error IRQ disable LCCR0_EFM 1 LCD end of frame IRQ disable LCCR0_PAS 1 LCD active display enable LCCR0_DPD 1 LCD send 8 pixel on L_DD[7:0] at each clock LCCR0_DIS 0 LCD controller disable LCCR0_QDM 1 LCD quick disable IRQ disable LCCR0_PDD 0 LCD palette DMA request delay LCCR0_BM 1 LCD branch start IRQ disable LCCR0_OUM 1 LCD fifo underrun IRQ disable LCD Controller Control Register 1 (7-26) LCCR1 0x03070cef 00000011 00000111 00001100 11101111 LCCR1_PPL 239 LCD pixels per line (+1) LCCR1_HSW 3 LCD horizontal sync pulse width (+1) LCCR1_ELW 7 LCD end of line pixel clock wait count (+1) LCCR1_BLW 3 LCD beginning of line pixel clock wait count (+1) LCD Controller Control Register 2 (7-28) LCCR2 0x04080d3f 00000100 00001000 00001101 00111111 LCCR2_LPP 319 LCD lines per panel (+1) LCCR2_VSW 3 LCD vertical sync pulse width (+1) LCCR2_EFW 8 LCD end of frame line clock wait count (+1) LCCR2_BFW 4 LCD beginning of frame line clock wait count (+1) LCD Controller Control Register 3 (7-31) LCCR3 0x04b00006 00000100 10110000 00000000 00000110 LCCR3_PCD 6 LCD pixel clock divisor (+1) LCCR3_ACB 0 LCD AC bias pin frequency (+1) LCCR3_API 0 LCD AC bias pin transitions per interrupt LCCR3_VSP 1 LCD L_FCLK vertical sync polarity active low LCCR3_HSP 1 LCD L_LCLK horizontal sync polarity active low LCCR3_PCP 0 LCD data sampled on falling edge of L_PCLK LCCR3_OEP 1 LCD L_BIAS output enable active low LCCR3_BPP 16 LCD bits per pixel LCCR3_DPC 0 LCD double pixel clock rate at L_PCLK FBR0 FBR0 0x00000000 00000000 00000000 00000000 00000000 LCD Controller Status Register (7-40) LCSR 0x00000010 00000000 00000000 00000000 00010000 LCD Controller Interrupt ID Register (7-41) LIIDR 0xe4126082 11100100 00010010 01100000 10000010 TMED RBG Seed Register (7-42) TRGBBR 0x00aa5500 00000000 10101010 01010101 00000000 TRGBBR_TRS 0 Red Seed TRGBBR_TGS 55 Green Seed TRGBBR_TBS aa Blue Seed TMED Control Register (7-44) TCR 0x0000754f 00000000 00000000 01110101 01001111 TCR_COAM 1 Color Offset Adjuster Matrix TCR_FNAM 1 Frame Number Adjuster Matrix TCR_COAE 1 Color Offset Adjuster Enable TCR_FNAME 1 Frame Number Adjuster Enable TCR_TVBS 4 Vertical Beat Suppression TCR_THBS 5 Horizontal Beat Suppression TCR_TED 1 Energy Distribution Matrix Select FDADR0 FDADR0 0xa1e80fe0 10100001 11101000 00001111 11100000 FSADR0 FSADR0 0xa1e87b40 10100001 11101000 01111011 01000000 FODR0 FIDR0 0x00000000 00000000 00000000 00000000 00000000 LDCMD0 LDCMD0 0x0001e560 00000000 00000001 11100101 01100000 FDADR1 FDADR1 0xa1e80fd0 10100001 11101000 00001111 11010000 FSADR1 FSADR1 0x00000000 00000000 00000000 00000000 00000000 FIDR1 FIDR1 0x00000000 00000000 00000000 00000000 00000000 LDCMD1 LDCMD1 0x00000000 00000000 00000000 00000000 00000000